參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 41/166頁
文件大小: 1145K
代理商: ARM966E-S
Initialization Control Signals
Rev. A
2-21
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
HCLKEN
HCLK Enable
HCLKEN is used in conjunction with CLK to effectively
run the ARM966E-S at a higher frequency than the AHB
system bus. HCLKEN is HIGH for a single CLK period
and signifies the rising edge of the AHB clock, HCLK. All
AHB outputs transition on the CLK rising edge in which
HCLKEN is asserted.
Input
nFIQ
Not Fast Interrupt
This active-LOW input is the ARM Fast interrupt request.
The ARM966E-S supports synchronous interrupts only.
Input
nIRQ
Not Interrupt Request
This active-LOW input is the ARM interrupt request. The
ARM966E-S supports synchronous interrupts only.
Input
2.9 Initialization Control Signals
INITRAM
RAM Enable Configuration
When INITRAM is HIGH, the Instruction and Data RAMs
are enabled at the end of reset. When it is LOW, the
Instruction and Data RAMs are disabled coming out of
reset.
Input
This input is a static configuration signal. Its value is
sampled at reset only.
VINITHI
High Vectors Configuration
When VINITHI is LOW at reset, the exception vectors
start at address 0x0000.0000. When VINITHI is HIGH,
the exception vectors start at 0xFFFF.0000.
Input
This signal is a static configuration signal. Its value is
sampled at reset only.
2.10 ATPG Scan Control Signals
SCANEN
Scan Enable
The ARM966E-S asserts this input HIGH to enable data
scanning through the scan chain.
Input
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