參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 51/166頁
文件大小： 1145K
代理商： ARM966E-S
Registers
Rev. A
3-9
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
User mode and System mode do not have an SPSR, as these modes
are not entered on any exception, so a register to preserve the CPSR is
not required. In User or System mode, any reads to the SPSR read an
unpredictable value, and any writes to the SPSR are ignored.
3.7.2 CP15 Registers
Use the MCR and MRC instructions to access the configuration
registers; the processor must be in supervisor (privileged) mode.
Never access an invalid CRn register because neither the access nor an
undefined instruction trap occurs. An access to a CRn register in user
mode causes the undefined instruction trap to be taken.
Table 3.4
Mode Bits
M[4:0]
Mode
Accessible Registers
0b10000
User
PC, R0 through R14, CPSR
0b10001
FIQ
PC, R0 through R7, R8_fiq through R14_fiq, CPSR, SPSR_fiq
0b10010
IRQ
PC, R0 through R12, R13_irq, R14_irq, CPSR, SPSR_irq
0b10011
SVC
PC, R0 through R12, R13_svc, R14_svc, CPSR, SPSR_svc
0b10111
Abort
PC, R0 through R12, R13_abt, R14_abt, CPSR, SPSR_abt
0b11011
Undef
PC, R0 through R12, R13_und, R14_und, CPSR, SPSR_und
0b11111
System
PC, R0 through R14, CPSR
Table 3.5
CP15 Register Map
Register
Function
0
ID Code
1
Control
2–6
Reserved
7
Core Control
8–12
Reserved
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