參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 15/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
Block Diagram Description
Rev. A
1-3
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
Figure 1.1
ARM966E-S Block Diagram
1.2.1 ARM9E-S Processor Core
The ARM9E-S processor core has a Harvard bus architecture with
separate instruction and data interfaces. This design allows concurrent
instruction and data accesses, and greatly reduces the cycles per
instruction of the processor. For optimal performance, single-cycle
memory accesses for both interfaces are required, although the core can
be stalled for nonsequential accesses or slower memory systems.
AHB Bus
Interface Unit
and
Write Buffer
Instruction
SRAM
Dout
Addr
Din
Data
SRAM
Dout
Addr
Din
System
Control
Coprocessor
(CP15)
External
Coprocessor
Interface
IA
ARM9E-S
Core
INSTR
RDATA
DA
WDATA
System
Controller
ETM
Interface
DMA Interface
DMA Controller
AHB Peripherals
Coprocessors
ETM
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