參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 105/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
Example SRAM Interfaces
Rev. A
8-9
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
an example of the most complex interface possible, Figure 8.5 assumes
that each byte-wide SRAM needs to be split into four blocks (see
word-wide SRAM in Section 8.5.2, “FOURSEGX32,”).
In Section 8.5.2, “FOURSEGX32,” the SRAM Address is 11 bits. Bits
[12:11] of the address are used to decode which of the four word-wide
RAMs is selected.
In Figure 8.5, ByteWrite[3:0] is used (inside
IRamIF.v
) to decode each
word-wide chip select into four separate chip select signals, one for each
byte of the word.
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