參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 60/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
3-18
Programmer’s Model
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
CP15 Data BIST Start/Pause Address Register –
The function of this
write-only register depends on the setting of the DPause bit in the CP15
BIST Control register.
When the Data BIST Pause bit is cleared, a write to this register
determines the Data BIST Start Address. BIST testing is executed on
data memory from DBIST Start Address to a function of the DBIST size
with respect to the Start Address. Normally, this register is cleared to
allow testing of the full data memory. However, it can be set to a nonzero
value to limit testing to only a portion of data memory.
When the Data BIST Pause bit is set, a write to this register sets the
Data Pause Address. When BIST testing is paused, the Pause address
is held at the data memory RAM address inputs.
CP15 Data BIST Test/Pause Write Data Register –
The function of
this write-only register depends on the setting of the DPause bit in the
CP15 BIST Control register.
When the Data BIST Pause bit is cleared, a write to this register sets the
Data BIST Data pattern (DBISTTestData). The BIST algorithm uses
DBISTTestData and its inverse pattern for data memory BIST testing.
When the Data BIST Pause bit is set and BIST operation is paused, data
written to this register is placed in the data memory at the DBIST Pause
Address.
CP15 Data BIST Fail Address Register –
This read-only register
contains the address of the first detected data memory failure. This
register is valid when the Data RAM BIST Fail bit is set in the CP15 BIST
Control register.
31
0
IBIST Fail Data/IBIST Pause Read Data
31
26 25
0
Reserved
DBIST Start Address/DBIST Pause Address
31
0
DBIST Test Data/DBIST Pause Write Data
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