參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數(shù): 100/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
8-4
Tightly Coupled RAM
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
accesses to the I-SRAM address space access the I-SRAM. Figure 3.2
on page 3-5 shows the I-SRAM address space.
Enabling the I-SRAM greatly increases the performance of the
ARM966E-S because most accesses to it have no stall cycles, whereas
accessing the ARM966E-S through the AHB can cause several stall
cycles for
each
access.
You must ensure that the I-SRAM is appropriately initialized before it is
enabled and used to supply instructions to the ARM966E-S. If the core
tries to execute instructions from uninitialized I-SRAM, the behavior is
unpredictable.
8.3.2.2 Disabling the I-SRAM
To disable the I-SRAM, clear bit 12 of the CP15 Control Register. When
the I-SRAM has been disabled, all further ARM966E-S instruction
fetches access the AHB. If the ARM966E-S performs a data access to
the I-SRAM address space, an AHB access is performed. Figure 3.2 on
page 3-5 shows the I-SRAM address space.
The contents of the I-SRAM are preserved when it is disabled. If it is
re-enabled, accesses to previously initialized I-SRAM locations returns
the preserved data.
8.3.2.3 Enabling the D-SRAM
To enable the D-SRAM, set bit 2 (the D bit) of the CP15 Control Register.
When the D-SRAM has been enabled, all future read and write accesses
to the D-SRAM address space cause the D-SRAM to be accessed.
Figure 3.2 on page 3-5 shows the D-SRAM address space.
8.3.2.4 Disabling the D-SRAM
To disable the D-SRAM, clear bit 2 of the CP15 Control Register. When
the D-SRAM is disabled, all further reads and writes to the D-SRAM
address space access the AHB. Figure 3.2 on page 3-5 shows the
D-SRAM address space. Read and write accesses to D-SRAM address
space use the D-SRAM (if enabled) or access the AHB.
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