參數(shù)資料
型號(hào)： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊(cè)6月1日
文件頁數(shù)： 130/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
10-14
Debug
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
10.5 ARM9E-S Clock Domains
The ARM9E-S clock, CLK, is qualified by two clock enables:
SYSCLKEN controls access to the memory system
DBGTCKEN controls debug operations
During normal operation, SYSCLKEN conditions CLK to clock the core.
When the ARM966E-S is in the debug state, DBGTCKEN conditions
CLK to clock the core.
10.6 Determining the Core and System States
When the ARM966E-S is in the debug state, you can examine the core
and system state by forcing the load and store multiples into the
instruction pipeline.
Before you can examine the core and system state, the debugger must
determine whether the processor entered debug from Thumb state or
ARM state, by examining bit 4 of the EmbeddedICE-RT Debug Status
Register. When bit 4 is HIGH, the core enters debug from Thumb state.
10.7 About the EmbeddedICE-RT Logic
The ARM9E-S EmbeddedICE-RT logic provides integrated on-chip
debug support for the ARM9E-S processor core.
EmbeddedICE-RT is programmed serially using the ARM9E-S TAP
controller. Figure 10.7 illustrates the relationship between the core,
EmbeddedICE-RT, and the TAP controller, showing only the signals that
are pertinent to EmbeddedICE-RT.
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