
CoreWare Program
Rev. A
1-7
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
The library also includes megafunctions or building blocks, which provide
useful functions for developing a system on a chip. Through the
CoreWare program, you can create a system on a chip uniquely suited
to your applications.
Each core has an associated set of deliverables, including:
Encrypted RTL or C simulation models for both Verilog and VHDL
environments
A System Verification Environment (SVE) for RTL-based simulation
Netlists for full timing simulation
Complete documentation
LSI Logic FlexStream
design support
The LSI Logic FlexStream design solution provides seamless
connectivity between products from leading Electronic Design
Automation (EDA) vendors and the LSI Logic manufacturing
environment. Standard interfaces for formats and languages such as
VHDL, Verilog, Waveform Generation Language (WGL), Physical Design
Exchange Format (PDEF), and Standard Delay Format (SDF) allow a
wide range of tools to interoperate within the LSI Logic FlexStream
design environment. In addition to design capabilities, full scan Automatic
Test Pattern Generation (ATPG) tools and LSI Logic's specialized test
solutions can be combined to provide high-fault coverage test programs
that assure a fully functional design.
Because your design requirements are unique, LSI Logic is flexible in
working with you to develop your system-on-a-chip CoreWare design.
Three different work relationships are available:
You provide LSI Logic with a detailed specification and LSI Logic
performs all design work.
You design some functions while LSI Logic provides you with the
cores and megafunctions, and LSI Logic completes the integration.
You perform the entire design and integration, and LSI Logic
provides the core and associated deliverables.
Whatever the work relationship, LSI Logic’s advanced CoreWare
methodology and ASIC process technologies consistently produce
Right-First-Time
silicon.