參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 34/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
2-14
Signal Descriptions
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
2.6 Debug Signals
COMMRX
Communications Channel Receive
When HIGH, this signal indicates that the Comms
Channel Receive Buffer has data that the ARM9E-S
processor core can read.
Output
COMMTX
Communications Channel Transmit
When HIGH, this signal indicates the Comms Channel
Transmit Buffer is empty.
Output
DBGACK
Debug Acknowledge
When HIGH, DBGACK indicates that the ARM9E-S
processor core is in debug mode.
Output
DBGDEWPT
Debug Watchpoint
This input can halt the processor for debug purposes. If
HIGH at the end of a data memory request cycle, this
input causes the ARM9E-S processor core to enter the
debug state.
Input
DBGEN
Debug Enable
A LOW on this input disables the debug features of the
ARM966E-S. Tie this input LOW when debugging is not
required.
Input
DBGEXT[1:0] Breakpoint/Watchpoint External Condition
These inputs to the EmbeddedICE logic make
breakpoints/watchpoints dependent on external
conditions.
Input
DBGIEBKPT
Processor Execution Breakpoint
When this input is asserted, processor execution is halted
for debug purposes. If DBGIEBKPT is HIGH at the end
of an instruction fetch, the ARM9E-S processor core
enters the debug state if that instruction reaches the
execute stage of the processor’s pipeline.
Input
DBGINSTREXEC
Instruction Executed
When this output is asserted HIGH, the instruction in the
execute stage of the processor’s pipeline was executed.
Output
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