參數資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數: 104/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
8-8
Tightly Coupled RAM
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
Figure 8.4
FOURSEGX32 Interface
Separate chip select signals are required for each SRAM block.
The generation of separate chip select signals for each SRAM block
ensures good power performance, because only the segment being
accessed is enabled.
The SRAM address is 11 bits in this example (compared with the 13
bit address in Section 8.5.1, “ONESEGX32”). RamAddr[12:11] are
used to generate separate chip selects for each segment.
If it is not possible to have separate chip select signals for each block of
RAM, for example, if the RAM is asynchronous, then separate write
enable signals are required for each segment. The use of asynchronous
RAMs is not recommended due to the increased power consumption of
this solution.
Note:
The wrapper RTL does not support asynchronous RAMs.
8.5.3 FOURSEGX8
Figure 8.5 shows that the SRAM needs to be split into four-byte wide
segments where an SRAM does not support byte writes. In order to give
ICtrl.v
IRamIF.v
2K x 32
ByteWrite[3:0]
RamAddr[10:0]
WriteEnable
ChipSelect[3:0]
2K x 32
2K x 32
2K x 32
IRData[31:0]
[2]
[3]
[127:96]
[95:64]
[1]
[0]
[63:32]
[31:0]
OutputSelect[1:0]
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