參數(shù)資料
型號(hào)： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊(cè)6月1日
文件頁數(shù)： 38/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
2-18
Signal Descriptions
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
ETMDMORE
ETM Sequential Data Indication
The ETMDMORE signal is active during load and store
multiple instructions and only goes HIGH when
ETMDnMREQ is LOW. This signal effectively gives the
same information as ETMDSEQ, but a cycle ahead. This
information is provided to allow external logic more time
to decode sequential cycles.
Output
ETMDnMREQ ETM Data Memory Request
This signal is asserted HIGH when the ARM966E-S is
making a request to the ETM data memory.
Output
ETMDnRW
ETM Data R/W
If this signal is LOW at the end of the cycle, then any data
memory access in the following cycle is a read. If this
signal is HIGH, then the access is a write.
Output
ETMDSEQ
ETM Sequential Data Indication
If this signal is HIGH at the end of the cycle, then any
data memory access in the following cycle is sequential
from the last data memory access.
Output
ETMEN
ETM Enable
When this signal is HIGH, the ETM is enabled and the
ARM966E-S interface signals are driven out of this
module, pipelined by one clock stage.
Input
ETMHIVECS
Exception Vector Location
When this output is LOW, the ARM966E-S exception
vectors start at address 0x0000.0000. When this signal is
HIGH, the ARM966E-S exception vectors start at address
0xFFFF.0000. This output is a static configuration signal.
Output
ETMIA[31:1]
ETM Instruction Address Bus
This 31-bit bus contains the address for the ETM.
Output
ETMID31To25[31:25]
Bits [31:25] of Instruction Data
These outputs reflect the status of bits [31:25] of the
instruction data read by the ARM966E-S.
Output
ETMID15To11[15:11]
Bits [15:11] of Instruction Data
These outputs reflect the status of bits [15:11] of the
instruction data read by the ARM966E-S.
Output
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