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10-20
Debug
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
10.9.4.2 Receiving a Message from the Debugger
Transferring a message from the debugger to the processor is similar to
sending a message to the debugger. In this case, the debugger polls the
R bit of the Debug Communications Control Register:
if the R bit is cleared, the Communications Data Read Register is
free for use, and data can be placed there for the processor to read
if the R bit is set, previously deposited data is not yet collected, so
the debugger must wait.
When the communications data read register is free, data is written there
using the JTAG interface. The action of this write sets the R bit in the
Debug Communications Control Register.
The processor polls the Debug Communications Control Register. If the
R bit is set, there is data that can be read using an MRC instruction to
CP14. The action of this load clears the R bit in the Debug
Communications Control Register. When the debugger polls this register
and sees that the R bit is cleared, the data is taken, and the process can
be repeated.
10.10 Real-Time Debug
The ARM9E-S processor within the ARM966E-S contains logic that
allows the debugging of a system without stopping the core entirely. Thus
critical interrupt routines can still be serviced while the core is being
interrogated by the debugger. Setting bit 4 of the Debug Control Register
enables the real-time debug features of the ARM9E-S. When bit 4 is set,
the EmbeddedICE-RT logic is configured so that a breakpoint or
watchpoint causes the ARM966E-S to enter abort mode, taking the
Prefetch Abort or Data Abort vectors, respectively. When the ARM966E-
S is configured for real-time debugging, you must be aware of the
following restrictions:
Breakpoints or watchpoints might not be data-dependent. No support
is provided for use of the range and chain functionalities. Breakpoints
or watchpoints can only be based on:
–
instruction or data addresses
–
external watchpoint conditioner (DBGEXTERN)