參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數(shù): 89/166頁
文件大小: 1145K
代理商: ARM966E-S
Slave Transfer Responses
Rev. A
5-19
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
5.7.3 Retry Responses
The RETRY response provides a mechanism for slaves to release the
bus when they are unable to supply data for a transfer immediately. This
mechanism allows the transfer to finish on the bus. Therefore a higher
priority ARM966E-S can get access to the bus.
After a RETRY has occurred, the arbiter continues to use the normal
priority scheme. Only masters that have a higher priority gain access to
the bus.
The ARM966E-S continues to request the bus and attempts the transfer
until it either has completed successfully or has been terminated with an
error response.
5.7.4 Split Responses
The SPLIT response provides a mechanism for slaves to release the bus
when they are unable to immediately supply data for a transfer. This
mechanism allows the transfer to finish on the bus. Therefore a higher
priority ARM966E-S can get access to the bus.
After a SPLIT has occurred, the arbiter adjusts the priority scheme so
that any other master requesting the bus gets access, even if it has a
lower priority. The slave requests access to the bus on behalf of the
master when the transfer can complete.
The ARM966E-S will continue to request the bus and attempt the transfer
until it is either completed successfully or terminated with an error
response.
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