參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數(shù): 121/166頁
文件大小: 1145K
代理商: ARM966E-S
About the Debug Interface
Rev. A
10-5
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
10.2.1 Stages of Debug
A request on one of the external debug interface signals or on an internal
functional unit known as the
EmbeddedICE-RT logic
forces the
ARM9E-S processor into the debug state. The interrupts that activate
debug are:
a breakpoint (a given instruction fetch)
a watchpoint (a data access)
an external debug request
The internal state of the ARM9E-S processor is examined using a
JTAG-style serial interface, allowing instructions to be serially inserted
into the pipeline without using the external data bus. For example, when
in the debug state, a Store Multiple instruction (STM) can be inserted into
the instruction pipeline, which exports the contents of the ARM966E-S
registers. This data can be serially shifted out without affecting the rest
of the system.
10.2.2 Clocks
The system and test clocks must be synchronized externally to the
ARM966E-S macrocell. The ARM Multi-ICE debug agent directly
supports one or more cores within an ASIC design. To synchronize
off-chip debug clocking with the ARM966E-S macrocell requires a
three-stage synchronizer. The off-chip device (for example, Multi-ICE)
issues a TCK signal, and then waits for the RTCK (Returned TCK) signal
to come back. Synchronization is maintained because the off-chip device
does not progress to the next TCK until after RTCK is received.
Figure 10.3 shows this synchronization logic.
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