參數(shù)資料
型號(hào)： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊(cè)6月1日
文件頁數(shù)： 132/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
10-16
Debug
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
Each watchpoint unit can be configured to be either a watchpoint
(monitoring data accesses) or a breakpoint (monitoring instruction
fetches). Watchpoints and breakpoints can be data-dependent.
10.8 Disabling the EmbeddedICE-RT Logic
To disable the EmbeddedICE-RT logic, force the DBGEN input LOW.
Hardwiring DBGEN LOW
permanently
disables debug access.
When DBGEN is LOW, it inhibits DBGDEWPT, DBGIEBKPT, and
EDBGRQ to the ARM9E-S, and DBGACK from the ARM966E-S is
always LOW.
10.9 The Debug Communications Channel
The EmbeddedICE-RT logic contains a communications channel for
passing information between the target and the host debugger. This
channel is implemented as coprocessor 14 (CP14).
The communications channel comprises:
a 32-bit communications data read register
a 32-bit communications data write register
a 6-bit communications control register for synchronized
handshaking between the processor and the asynchronous
debugger.
These registers are located in fixed locations in the EmbeddedICE-RT
logic register map and are accessed from the processor using MCR and
MRC instructions to CP14.
In addition to the communications channel registers, the processor can
access a one-bit Debug Status Register for use in the real-time debug
configuration.
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