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| 型號： | ARM966E-S |
| 英文描述： | ARM966E-S Microprocessor Core preliminary technical manual 6/01 |
| 中文描述： | ARM966E - ?微處理器核的初步技術(shù)手冊6月1日 |
| 文件頁數(shù)： | 82/166頁 |
| 文件大小： | 1145K |
| 代理商： | ARM966E-S |
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5-12
AHB Interface Unit
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
When a master is granted the bus, its address and control signals are
driven to all slaves. These signals provide information on the address,
direction, and width of the transfer, as well as an indication when the
transfer forms part of an incrementing burst. Incrementing bursts do not
wrap at address boundaries.
A write data bus moves data from the master to a slave, while a read
data bus moves data from a slave to the master.
Every transfer consists of an address/control cycle followed by one or
more cycles for the data. The address cannot be extended and therefore
all slaves must sample the address during this time. The data, however,
can be extended using the HREADY signal. When LOW, this signal
causes wait states to be inserted into the transfer and allows extra time
for the slave to provide or sample data.
During a transfer, the slave shows the status using the response signals,
HRESP[1:0]. The OKAY response indicates that the transfer is
progressing normally, and, when HREADY goes HIGH, shows the
transfer has completed successfully.
The other possible transfer responses are ERROR, RETRY, and SPLIT.
The ERROR response indicates that a transfer error occurred and the
transfer was unsuccessful. Both SPLIT and RETRY transfer responses
indicate that the transfer cannot complete immediately, but the bus
master should continue to attempt the transfer.
In normal operation, a master is allowed to complete all the transfers in
a particular burst before the arbiter grants another master access to the
bus. However, in order to avoid excessive arbitration latencies, it is
possible for the arbiter to break up a burst and in such cases, the master
must rearbitrate for the bus in order to complete the remaining transfers
in the burst.
5.5 Basic Transfers
An AHB transfer consists of two distinct sections, the address and the
data. The address lasts only a single cycle, while the data might require
several cycles, using the HREADY signal.
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