參數(shù)資料
型號(hào)： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 53/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
Registers
Rev. A
3-11
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
cleared to zero on reset unless stated otherwise. The reserved bits have
an unpredictable value when read.
Res (SBZ)
Reserved
These bits are reserved and must be written as zeros.
[31:16], 14, [11:8], [1:0]
TBIT
Configure Disable Loading TBIT
This bit controls the behavior of load PC instructions.
When TBIT is cleared, a load to the PC uses bit 0 of the
loaded data to control the entry into the THUMB state.
When TBIT is set, this behavior is disabled. At reset, this
bit is cleared.
15
V
Alternate Vector Select
This read-only bit controls the base address used for the
exception vectors. When V is cleared, the base address
for the exception vectors is 0x0000.0000. When V is set,
the base address for the exception vectors is
0xFFFF.0000. At reset, this bit takes on the value of the
VINITHI pin.
13
I
Instruction Memory Enable Bit
When this bit is set, all accesses to the Instruction
memory space will access the Instruction RAM. When
this bit is cleared, all accesses to the Instruction Memory
space will access the AHB. At reset, this bit takes on the
value of the INITRAM pin.
12
E
Big/Little Endian Bit
This bit determines the byte-ordering convention. It is
cleared during reset.
7
Res (SBO)
Reserved
These bits are reserved and must be written as ones.
[6:4]
31
16
15
14
13 12 11
8
7
6
4
3
2
1
0
Res (SBZ)
TBIT
(Res
I
Res (SBZ)
E
Res
(SBO)
W
B
D
Res
(SBZ)
E
Endian
0
1
Little Endian
Big Endian
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