參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數(shù): 126/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
10-10
Debug
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
Figure 10.4 Breakpoint Timing
10.4.2 Breakpoints and Exceptions
A breakpointed instruction can have a Prefetch Abort associated with it.
If so, the Prefetch Abort takes priority and the breakpoint is ignored.
(If there is a prefetch abort, instruction data might be invalid, the
breakpoint might be data-dependent, and if the data is incorrect, the
breakpoint could have triggered incorrectly.)
SWI and undefined instructions are treated the same as any other
instruction with a breakpoint set on it. Therefore the breakpoint takes
priority over the SWI or undefined instruction.
On an instruction boundary, if there is a breakpointed instruction and an
interrupt (nIRQ or nFIQ), the interrupt is taken and the breakpointed
instruction is discarded. When the interrupt is being serviced, the
execution flow is returned to the original program. Thus the instruction
that was previously breakpointed is fetched again, and if the breakpoint
is still set, the processor enters the debug state when it reaches the
Execute stage of the pipeline.
When the processor enters the halt-mode debug state, it is important that
further interrupts do not affect the instructions executed. For this reason,
as soon as the processor enters the stop-mode debug state, interrupts
are disabled, although the state of the I and F bits in the Program Status
Register (PSR) are not affected.
F1
D1
F2
E1
D2
F1
M1
E2
D1
Ddebug
W1
M2
E1
Edebug1
W2
M1
Edebug2
W1
2
1
3
4
CLK
IA[31:1]
INSTR[31:0]
DBGIEBKPT
DBGACK
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