參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數(shù): 44/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
3-2
Programmer’s Model
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
The CP15 registers are accessible with MCR and MRC instruction.
These registers are defined in Section 3.7.2, “CP15 Registers.”
Any coprocessors and their registers that are attached to the external
coprocessor interface are accessible with the appropriate coprocessor
instructions.
3.2 Data Abort Model
The ARM966E-S implements the
base restored data abort model
, which
differs from the
base updated data abort model
implemented by the
ARM7TDMI. The difference in the Data Abort model affects only a very
small section of operating system code, the Data Abort handler. It does
not affect user code.
With the base restored data abort model, when a Data Abort exception
occurs during the execution of a memory access instruction, the
processor hardware always restores the base register to the value the
register contained
before
the instruction was executed. This step
removes the requirement for the Data Abort handler to
unwind
any base
register update that might have been specified by the aborted instruction.
The base restored data abort model significantly simplifies the software
Data Abort handler.
3.3 Data Types
The ARM966E-S supports the data types listed in Table 3.1.
Table 3.1
Supported Data Types
Data Type
Size
Byte
8 bits
Halfword
16 bits (halfwords must be aligned to two-byte boundaries)
Word
32 bits (words must be aligned to four-byte boundaries)
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