82815 GMCH
R
96
Datasheet
3.5.18.
MLIMIT—Memory Limit Address Register (Device 1)
Address Offset:
22–23h
Default Value:
0000h
Access:
Read/Write
Size:
16 bits
This register controls the processor to PCI1 non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE
≤
address
≤
MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes when read. The
configuration software must initialize this register. For the purpose of address decode, address bits
A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1 MB aligned memory block.
15
4
3
0
Memory Address Limit
Reserved
Bit
Description
15: 4
Memory Address Limit (MEM_LIMIT).
Corresponds to A[31:20] of the memory address. (Default=0)
3:0
Reserved.
Note:
Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable
PCI1/AGPaddress ranges (typically, where control/status memory-mapped I/O data structures of the
graphics controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address
ranges (typically, graphics local memory). This segregation allows application of USWC space attribute
to be performed in a true plug-and-play manner to the prefetchable address range for improved processor
–AGP memory access performance.
Note:
Configuration software is responsible for programming all address range registers (prefetchable, non-
prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with each other
and/or with the ranges covered with the main memory). There is no provision in the GMCH hardware to
enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed.