參數(shù)資料
型號： FW82815
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 45/172頁
文件大?。?/td> 795K
代理商： FW82815
82815 GMCH
R
Datasheet
45
3.4.3.
PCICMD—PCI Command Register (Device 0)
Address Offset:
Default:
Access:
Size:
04–05h
0006h
Read/Write
16 bits
This register provides basic control over the PCI0 interface (hub interface) ability to respond to PCI
cycles. The PCICMD Register enables and disables the SERR# signal, parity checking (PERR# signal),
GMCH’s response to PCI special cycles, and enables and disables PCI0 bus master accesses to main
memory.
15
10
9
8
Reserved (0)
FB2B
(Not Impl)
SERR En
7
6
5
4
3
2
1
0
Addr/Data
Stepping
(Not Impl)
Parity
Error En
(Not Impl)
VGA Pal
Sn
(Not Impl)
Mem WR
& Inval En
(Not Impl)
Special
Cycle En
(Not Impl)
Bus
Master En
(Not Impl)
Mem Acc
En
(Not Impl)
I/O Acc En
(Not Impl)
Bit
Descriptions
15:10
Reserved.
9
Fast Back-to-Back. (Not implemented).
Hardwired to 0. Selects whether the GMCH can generate
fast back-to-back transactions to different PCI targets.
8
SERR Enable (SERRE)
. This bit is a global enable bit for Device 0 SERR messaging. The GMCH
does not have an SERR# signal. The GMCH communicates the SERR# condition by sending an SERR
message to the I/O Controller Hub.
1 = Enable. GMCH is enabled to generate SERR messages over the Hub interface for specific Device
0 error conditions
0 = Disable. SERR message is not generated by the GMCH for Device 0.
NOTE:
This bit only controls SERR messaging for Device 0. Device 1 has its own SERRE bit to
control error reporting for error conditions occurring on Device 1. The two control bits are used
in a logical OR manner to enable the SERR hub interface message mechanism.
7
Address/Data Stepping. (Not implemented).
Hardwired to 0.
6
Parity Error Enable (PERRE). (Not implemented).
Hardwired to 0. PERR# is not implemented by
GMCH. Writes to this bit position have no affect.
5
VGA Palette Snoop.
(Not implemented).
Hardwired to 0. Writes to this bit position have no affect.
4
Memory Write and Invalidate Enable.
The GMCH will never use this command and this bit is
hardwired to 0. Writes to this bit position will have no affects.
3
Special Cycle Enable.
(Not implemented).
Hardwired to 0. The GMCH ignores all special cycles
generated on the PCI.
2
Bus Master Enable (BME)
.
(Not implemented).
Hardwired to 1. The GMCH is always allowed to be a
Bus Master. . Writes to this bit position have no affect.
1
Memory Access Enable (MAE)
.
(Not implemented).
Hardwired to 1. The GMCH always allows
access to main memory. Writes to this bit position have no affect.
0
I/O Access Enable (IOAE)
.
(Not implemented).
Hardwired to 0. Writes to this bit position have no
affect.
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