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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 51/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
51
3.4.14.
GMCHCFG—GMCH Configuration Register (Device 0)
Address Offset:
50h
Default:
01ss0s00
Access:
Read/Write, Read-Only
Size:
8 bits
7
6
5
4
3
2
1
0
Mem Arb
Gnt Win
Enable
CPU
Latency
Timer
Reserved
Local
Memory
Frequency
Select
DRAM
Page
Closing
Policy
System
Memory
Frequency
Select
Reserved
Bit
Description
7
Memory Arbiter Grant Window Enable (MAGWE).
This bit controls the Host vs Low Priority Graphics
timeslice regulation in the arbiter for the System DRAM.
At pre-arbitration (aka, stage 1)
0 = Disabled. Enforce fixed priority.
1 = Limit grant to host-to-graphics stream to 6 consecutive packets.
At main-arbitration (aka, stage 2)
0 = Disabled. Enforce fixed priority.
1 = 24 clocks limiting host, 24 clocks guaranteed to low priority graphics stream.
In fixed mode arbitration (MAGWE=0) the host stream always has higher priority over the low priority
graphics stream for accesses to system memory. In timeslice mode, the host stream and the low
priority graphics stream are both regulated by a time window to provide fairness to the graphics stream.
Fixed priority mode, where the host stream is always favored, is the recommended mode of operation;
this setting gives highest system performance without adversely affecting graphics performance under
real life applications workload.
6
CLT (CPU Latency Timer).
0 = Deferrable processor cycle will be Deferred immediately after receiving another ADS#
1 = Deferrable processor cycle will only be Deferred after in has been held in a “Snoop Stall” for 31
clocks and another ADS# has arrived (default).
5
Reserved.
4
Local Memory Frequency Select (LMFS).
This bit selects the operating frequency for the Local
Memory Controller. Default is set by sampling the LM_FREQ_SEL strap (AGP SBA[7] pin) at reset. It
has a weak internal pull-up enabled during reset.
This is a reserved bit in the UMA Only and No Internal Graphics SKUs. A 0 is read back in these SKUs.
The output of the register bit in these SKUs is also forced to 0 such that a customer cannot effectively
program the part for 133 MHz local memory. In the Fully-Featured and 100 MHz FSB & SM SKUs,
either 1 or 0 can be programmed by the customer.
1 = 133 MHz, (default). This is a reflection of LM_FREQ_SEL strap being pulled up (default).
0 = 100 MHz. This is a reflection of LM_FREQ_SEL strap being pulled down.
Note.
The value of this bit should only be changed when the Internal Graphics device is disabled
(i.e., GMS = 00).
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| FW82815SL5NQ | 制造商:Intel 功能描述: |
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