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82815 GMCH
R
66
Datasheet
3.4.23.
CAPID—Capability Identification (Device 0: AGP Mode Only)
Address Offset:
88–8Bh
Default Value:
F104 A009h
Access:
Read-Only
Size:
32 bits
This register
uniquely identifies chipset capabilities as defined in the table
below. Writes to this register have no effect.
31
30
29
28
27
24
133 MHz
Capability
Display
Cache
Capability
AGP
Capability
Internal
Graphics
Capability
CAPID Version
23
16
CAPID Length
15
8
Next Capability Pointer
7
0
CAP_ID
Bit
Description
31
133 MHz Capability—RO.
0 = Component is capable of up to 100 MHz front side bus and system memory.
1 = Component is capable of up to 133 MHz front side bus and system memory.
30
Display Cache Capability—RO.
0 = Only supports UMA mode (no local memory).
1 = Component is local memory (Display Cache) and UMA capable.
29
AGP Capability—RO.
0 = AGP mode not supported. Note that the AGP interface may still be active through the addition of
an AIMM card if bits 28 and 30 are both 1.
1 = AGP mode supported.
28
Internal Graphics Capability—RO.
0 = Internal graphic controller not supported.
1 = Internal graphic controller supported.
27:24
CAPID Version—RO.
This field has the value 0001b to identify the first revision of the CAPID register
definition.
23:16
CAPID Length—RO.
This field has the value 04h to indicate the structure length.