82815 GMCH
R
74
Datasheet
3.4.29.
AGPSTAT—AGP Status Register (Device 0: AGP Mode Only)
Address Offset:
A4–A7h
Default Value:
1F000207h
Access:
Read-Only
Size:
32 bits
This register reports AGP device capability/status.
31
24
Request Queue (RQ) (HW=1Fh)
23
16
Reserved
15
10
1
8
Reserved
SBA
(HW=1)
Reserved
7
6
5
4
3
2
0
Reserved
>4 GB
Support
(HW=0)
Fast
Writes
(HW=0)
Reserved
Data Transfer Rate
(HW=111; 1x,2x,4x modes supported)
Bit
Description
31:24
Request Queue (RQ).
This field is hardwired to 1Fh to indicate a maximum of 32 outstanding AGP
command requests can be handled by the GMCH. This field contains the maximum number of AGP
command requests the GMCH is configured to manage. The lower 6 bits of this field reflect the value
programmed in AGPCTRL[12:10]. Only discrete values of 32, 16, 8, 4 , 2 and 1 can be selected via
AGPCTRL. Upper bits are hardwired to 0.
Default =1Fh to allow a maximum of 32 outstanding AGP command requests.
23:10
Reserved
9
SideBand Addressing (SBA).
Indicates the GMCH supports sideband addressing. Hardwired to 1.
8:6
Reserved
5
Greater Than 4 GB Address Support (4GB).
This bit indicates that the GMCH does
not
support
addresses greater than 4 GB. It is hardwired to 0.
4
Fast Writes (FW).
This bit indicates that the GMCH does
not
support Fast Writes from the processor
to the AGP master. It is hardwired to a 0.
3
Reserved
2:0
Data Transfer Rate Capability (RATE).
After reset the GMCH reports its data transfer rate capability.
Note that the selected data transfer mode applies to both AD bus and SBA bus.
Bit 0 = 1 = 1x data transfer mode
Bit 1 = 1 = 2x data transfer mode
Bit 2 = 1 = 4x data transfer mode. This bit can be masked by the AGPCTRL register bit 0
(AGP 4X Override).
1x , 2x , and 4x data transfer modes are supported by the GMCH; therefore, this bit field has a
Default
Value = 111.