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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 131/172頁(yè) |
| 文件大小： | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
131
4.3.2.1.
AGP Interface Decode Rules
Cycles Initiated Using PCI Protocol
The GMCH does not support any AGP/PCI access targeting the hub interface. The GMCH will claim
AGP/PCI initiated memory read and write transactions decoded to the main DRAM range or the graphics
Aperture range. All other memory read and write requests will be master-aborted by the AGP/PCI
initiator as a consequence of the GMCH not responding to a transaction.
Under certain conditions, the GMCH restricts access to the DOS compatibility ranges governed by the
PAM registers by distinguishing access type and destination bus. The GMCH accepts AGP/PCI write
transactions to the compatibility ranges if the PAM designates DRAM as write-able. If accesses to a
range are not write enabled by the PAM, the GMCH does not respond and the cycle results in a master-
abort. AGP/PCI read transactions to the compatibility ranges are accepted if the PAM designates DRAM
as readable. If accesses to a range are not read enabled by the PAM, the GMCH does not respond and the
cycle will result in a master-abort.
If agent on AGP/PCI issues an I/O or PCI Special Cycle transaction, the GMCH does not respond and
cycle results in a master-abort. The GMCH does not accept PCI configuration cycles to the internal
GMCH devices.
Cycles Initiated Using AGP Protocol
All cycles must reference main memory—main DRAM address range (
excluding
PAM) or graphics
aperture range (also physically mapped within DRAM but using different address range). AGP accesses
to the PAM region from 640 KB –to- 1 MB are not allowed. AGP accesses to SMM space are not
allowed. AGP-initiated cycles that target DRAM are not snooped on the host bus, even if they fall
outside of the AGP aperture range.
If a cycle is outside of a valid main memory range, then it will terminate as follows:
Reads: Remap to memory address 0h, return data from address 0h, and set the IAAF error flag.
Writes: Remapped to memory address 0h with byte enables deasserted (effectively dropped “on the
floor”) and set the IAAF error flag.
AGP Accesses to GMCH that CrosbvDevice Boundaries
For FRAME# accesses, when an AGP or PCI master gets disconnected, it will resume at the new address
that allows the cycle to be routed to or claimed by the new target. Therefore, accesses should be
disconnected by the target on potential device boundaries. The GMCH disconnects AGP/PCI
transactions on 4 KB boundaries.
AGP PIPE# and SBA accesses are limited to 256 bytes and must hit DRAM. AGP accesses are
dispatched to DRAM on naturally aligned 32-byte block boundaries. The portion of the request that hits
a valid address completes normally. The portion of a read access that hits an invalid address is remapped
to address 0h, returns data from address 0h, and sets the IAAF error flag. The portion of a write access
that hits an invalid address is remapped to memory address 0h with byte enables deasserted (effectively
dropped “on the floor”) and set the IAAF error flag.
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| FWA-25A10F | Fuse |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
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