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82815 GMCH
R
58
Datasheet
Table 4. Attribute Bit Assignments
Bits [7, 3]
Reserved
Bits [6, 2]
Reserved
Bits [5, 1]
WE
Bits [4, 0]
RE
Description
X
X
0
0
Disabled.
DRAM is disabled and all accesses
are directed to the hub interface. The GMCH
does not respond as a AGP/PCI or hub
interface target for any read or write access to
this area.
X
X
0
1
Read-Only
. Reads are forwarded to DRAM
and writes are forwarded to the hub interface
for termination. This write protects the
corresponding memory segment. The GMCH
responds as a AGP/PCI or hub interface
target for read accesses but not for any write
accesses.
X
X
1
0
Write Only
. Writes are forwarded to DRAM
and reads are forwarded to the hub interface
for termination. The GMCH responds as a
AGP/PCI or hub interface target for write
accesses but not for any read accesses.
X
X
1
1
Read/Write
. This is the normal operating
mode of main memory. Both read and write
cycles from the host are claimed by the
GMCH and forwarded to DRAM. The GMCH
responds as a AGP/PCI or hub interface
target for both read and write accesses.
As an example, consider a BIOS that is implemented on the expansion bus. During the initialization
process, BIOS can be shadowed in main memory to increase the system performance. When BIOS is
shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the
attributes for that address range should be set to write only. BIOS is shadowed by first doing a read of
that address. This read is forwarded to the expansion bus. The host then does a write of the same address,
which is directed to main memory. After BIOS is shadowed, the attributes for that memory area are set to
read-only so that all writes are forwarded to the expansion bus. The table above and the figure below
show the PAM registers and the associated attribute bits.