參數(shù)資料
型號(hào)： FW82815
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 100/172頁
文件大?。?/td> 795K
代理商： FW82815
82815 GMCH
R
100
Datasheet
Bit
Description
3
VGA Enable.
This bit works with the MDA present bit (GMCHCFG[3]) of device 0 to control the routing
of processor-initiated transactions targeting VGA compatible I/O and memory address ranges. When
this bit is set, the GMCH forwards the following processor accesses to the AGP:
Memory accesses in the range 0A0000h to 0BFFFFh
I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(inclusive of ISA address aliases – A[15:10] are not decoded)
1 = Enable. Forwarding of these accesses issued by the processor is independent of the I/O address
and memory address ranges defined by the previously defined Base and Limit registers.
Forwarding of these accesses is also independent of the settings of bit 2 (ISA Enable) of this
register if this bit is 1. If the VGA enable bit is set, accesses to IO address range x3BCh–x3BFh are
forwarded to the hub interface. If the VGA enable bit is not set, accesses to IO address range
x3BCh–x3BFh are treated just like any other IO accesses (i.e., cycles are forwarded to AGP, if the
address is within IOBASE and IOLIMIT and ISA enable bit is not set; otherwise, they are forwarded
to hub interface).
0 = Disable (default). VGA compatible memory and I/O range accesses are not forwarded to AGP;
rather, they are mapped to primary PCI unless they are mapped to AGP via I/O and memory range
registers defined above (IOBASE, IOLIMIT, MBASE, MLIMIT, PMBASE, PMLIMIT).
The following table shows the behavior for all combinations of MDA and VGA:
VGA
MDA
Behavior
0
0
1
0
1
0
All references to MDA and VGA Go To hub interface
Illegal combination (DO NOT USE)
All references To VGA Go To AGP MDA-only references (I/O Address 3BF
and aliases) will go to hub interface.
VGA references go to AGP/PCI; MDA references go to the hub interface
1
1
2
ISA Enable.
Modifies the response by the GMCH to an I/O access issued by the processor that targets
ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT
registers.
1 = Enable. GMCH will not forward to PCI1/AGP any I/O transactions addressing the last 768 bytes in
each 1 KB block, even if the addresses are within the range defined by the IOBASE and IOLIMIT
registers. Instead of going to PCI1/AGP, these cycles are forwarded to the hub interface where
they can eventually be subtractively or positively claimed by the ISA bridge.
0 = Disable (default). All addresses defined by the IOBASE and IOLIMIT for processor I/O transactions
are mapped to PCI1/AGP.
1
SERR# Enable.
Hardwired to 0. This bit normally controls forwarding SERR# on the secondary
interface to the primary interface.
The GMCH does not support the SERR# signal on the AGP/PCI1
bus.
0
Parity Error Response Enable.
Controls GMCH’s response to data phase parity errors on PCI1/AGP.
G_PERR# is not implemented by the GMCH.
1 = Enable. Address and data parity errors on PCI1 are reported via SERR messaging, if enabled by
SERRE1.
0 = Disable. Address and data parity errors on PCI1/AGP are not reported via SERR messaging. Other
types of error conditions can still be signaled via SERR messaging independent of this bit’s state.
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