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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 55/172頁(yè) |
| 文件大小： | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
55
3.4.17.
DRAMT—DRAM Timing Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
53h
00h
Read/Write
8 bits
This register controls the operating mode and the timing of the DRAM Controller.
7
5
4
3
2
1
0
SDRAM Mode Select
DRAM
Cycle
Time
Intel
Reserved
CAS#
Latency
SDRAM
RAS# to
CAS# Dly
SDRAM
RAS#
Precharge
Bit
Description
7:5
SDRAM Mode Select (SMS).
These bits select the operational mode of the GMCH DRAM interface.
The special modes are intended for initialization at power up.
000 =
DRAM in Self-Refresh Mode
, Refresh Disabled (Default)
001 =
Normal
Operation, 100 MHz System memory – Refresh interval 15.6 uSec
133 MHz System memory – Refresh interval 11.7 uSec
010 =
Normal
Operation, 100 MHz System memory – Refresh interval 7.8
133 MHz System memory – Refresh interval 5.85 uSec
011 =
Normal
Operation, 100 MHz System memory – Refresh interval 1.28 uSec
133 MHz System memory – Refresh interval 0.96 uSec
100 =
NOP Command Enable.
In this mode all processor cycles to SDRAM result in a NOP
Command on the SDRAM interface.
101 =
All Banks Precharge Enable.
In this mode all processor cycles to SDRAM result in an All
Banks Precharge Command on the SDRAM interface.
110 =
Mode Register Set Enable.
In this mode all processor cycles to SDRAM result in a mode
register set command on the SDRAM interface. The Command is driven on the MA[12:0] lines.
MA[2:0] must always be driven to 010 for burst of 4 mode. MA3 must be driven to 1 for
interleave wrap type. MA4 needs to be driven to the value programmed in the CAS# Latency bit.
MA[6:5] should always be driven to 01. MA[12:7] must be driven to 00000. BIOS must calculate
and drive the correct host address for each row of memory such that the correct command is
driven on the MA[12:0] lines.
Note that MAB[7:4]# are inverted from MAA[7:4]; BIOS must account for this.
111 =
CBR Enable.
In this mode all processor cycles to SDRAM result in a CBR cycle on the SDRAM
interface.
4
DRAM Cycle Time (DCT).
This bit controls the number of SCLKs for an access cycle.
0 = Tras = 5 SCLKs and Trc = 7 SCLKs (Default)
1 = Tras = 7 SCLKs and Trc = 9 SCLKs.
3
Intel Reserved.
2
CAS# Latency (CL).
This bit controls the number of CLKs between when a read command is sampled
by the SDRAMs and when GMCH samples read data from the SDRAMs.
0 = CAS# latency is 3 SCLKs.
1 = CAS# latency is 2 SCLKs.
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