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參數(shù)資料
| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 144/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
144
Datasheet
4.8.
Internal Graphics Device
4.8.1.
3D/2D Instruction Processing
The GMCH contains an extensive set of instructions that control various functions including 3D
rendering, BLT and STRBLT operations, display, motion compensation, and overlay. The 3D
instructions set 3D pipeline states and control the processing functions. The 2D instructions provide an
efficient method for invoking BLT and STRBLT operations.
The graphics controller executes instructions from one of two instruction buffers located in system
memory: Interrupt Ring or Low Priority Ring. Instead of writing instructions directly to the GMCH’s
graphics controller, software sets up instruction packets in these memory buffers and then instructs the
GMCH to process the buffers. The GMCH uses DMAs to put the instructions into its FIFO and executes
them. Instruction flow in the ring buffer instruction stream can make calls to other buffers, much like a
software program makes subroutine calls. Flexibility has been built into the ring operation permitting
software to efficiently maintain a steady flow of instructions.
Batching instructions in memory ahead of time and then instructing the graphics controller to process the
instructions provides significant performance advantages over writing directly to FIFOs including: 1)
Reduced software overhead, 2) Efficient DMA instruction fetches from graphics memory, and 3)
Software can more efficiently set up instruction packets in buffers in graphics memory (faster than
writing to FIFOs).
Figure 8. 3D/2D Pipeline Preprocessor
DMA
FIFO
Instr
Parser
3D Instructions (3D state,
3D Primitives, STRBLT,
Motion Compensation)
2D Instructions
cmd_str.vsd
3D
Engine
BLT
Engine
Instruction access and decoding
Low Priority Ring
(Graphics Memory)
Instruction
Batch Buff Instr
Instruction
Batch Buffers
Display
Engine
Overlay
Engine
Interrupt Ring
(Graphics Memory)
Instruction
Batch Buff Instr
Instruction
Batch Buffers
DMA
DMA
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PDF描述 |
|---|---|
| FWA-25A10F | Fuse |
| FWA-30A10F | Fuse |
| FWA-35A21F | Fuse |
| FWA-40A21F | Fuse |
| FWA-45A21F | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
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