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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 140/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
140
Datasheet
4.5.4.
SDRAMT Register Programming
Several DRAM timing parameters are programmable in the GMCH configuration registers. Table 16
summarizes the programmable parameters.
Table 16. Programmable SDRAM Timing Parameters
Parameter
DRAMT Bit
Values (SCLKs)
RAS# Precharge (SRP)
0
2,3
RAS# to CAS# Delay (SRCD)
1
2,3
CAS# Latency (CL)
2
2,3
DRAM Cycle Time (DCT)
4
Tras = 5,6
Trc = 7,8
These parameters are controlled via the DRAMT register. To support different device speed grades,
CAS# Latency, RAS# to CAS# Delay, and RAS# Precharge are all programmable as either two or three
SCLKs. To provide flexibility, these are each controlled by separate register bits (i.e., the GMCH can
support any combination of CAS# Latency, RAS#-to-CAS# Delay and RAS# Precharge).
4.5.5.
SDRAM Paging Policy
The GMCH can maintain up to 4 active pages in any one row; however, the GMCH does not support
active pages in more than 1 row at a time.
The DRAM page closing policy (DPCP) in the GMCH configuration register (GMCHCFG) controls the
page closing policy of the GMCH. This bit controls whether the GMCH “precharges bank” or
“precharges all” during the service of a page miss. When this bit is 0, the GMCH prechanges bank during
the service of a page miss. When this bit is 1, the GMCH prechanges all during the service of a page
miss.
4.6.
Intel
Dynamic Video Memory Technology (D.V.M.T.)
The internal graphics device on the GMCH supports Intel
Dynamic Video Memory Technology
(D.V.M.T.). D.V.M.T. dynamically responds to application requirements by allocating the proper
amount of display and texturing memory. For more details, refer to the document entitled
, “Intel
810
Chipset: Great Performance for Value PCs”
available at:
http://developer.intel.com/design/chipsets/810/810white.htm.
In addition to D.V.M.T., the GMCH supports Display Cache (DC). The graphics engine of the GMCH
uses DC for implementing rendering buffers (e.g., Z buffers). This rendering model requires 4 MB of
display cache and allows graphics rendering (performed across the graphics display cache bus) and
texture MIP map access (performed across the system memory bus) simultaneously. In using D.V.M.T.,
all graphics rendering is implemented in system memory. The system memory bus is arbitrated between
texture MIP-map accesses and rendering functions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FWA-25A10F | Fuse |
| FWA-30A10F | Fuse |
| FWA-35A21F | Fuse |
| FWA-40A21F | Fuse |
| FWA-45A21F | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
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