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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 81/172頁(yè) |
| 文件大小： | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
81
3.4.36.
GMCHCFG—GMCH Configuration Register
(Device 0: AGP Mode Only)
Address Offset:
Default:
Access:
Size:
BEh
0000 X000b
Read/Write, Read-Only
8 bits
7
6
5
4
3
2
0
Reserved
MDA
Present
(R/W)
Reserved
AGP_BUF
Mode
(RO)
Reserved
Bit
Description
7:6
Reserved.
5
MDA Present (MDAP)—R/W.
This bit works with the VGA Enable bit in the BCTRL register (3Eh, bit 3)
of device 1 to control the routing of processor-initiated transactions targeting MDA compatible I/O and
memory address ranges. This bit should not be set when the VGA Enable bit is not set. If the VGA
enable bit is set, accesses to IO address range x3BCh–x3BFh are forwarded to the hub interface. If the
VGA enable bit is not set, accesses to IO address range x3BCh–x3BFh are treated just like any other IO
accesses (i.e., the cycles are forwarded to AGP if the address is within IOBASE and IOLIMIT, and the
ISA enable bit is not set; otherwise, they are forwarded to the hub interface). MDA resources are defined
as the following:
Memory:
0B0000h–0B7FFFh
I/O:
(including ISA address aliases, A[15:10] are not used in decode)
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to the
hub interface, even if the reference includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGA
MDA
Behavior
0
0
All references to MDA and VGA go to hub interface
0
1
Illegal combination (DO NOT USE)
1
0
All references to VGA go to AGP/PCI. MDA-only references (I/O address 3BFh and
aliases) will go to the hub interface.
1
1
VGA references go to AGP/PCI; MDA references go to the hub interface.
4
Reserved.
3
AGP I/O Buffer Mode (AGP_BUF)—RO.
The GMCH has an internal circuit that detects the voltage
level on the AGP I/O buffer VDDQ rail. The voltage level information is latched 500 us after the
deasserting edge of RSTIN# and stored in this register bit.
1 = AGP VDDQ is sensed at 3.3V.
0 = AGP VDDQ is sensed at 1.5V.
2:0
Reserved.
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