82815 GMCH
R
110
Datasheet
3.6.14.
MMADR—Memory Mapped Range Address Register (Device 2)
Address Offset:
14
17h
Default Value:
00000000h
Access:
Read/Write, Read-Only
Size:
32 bits
This register requests allocation for the GMCH registers and instruction ports. The allocation is for
512 KB and the base address is defined by bits [31:19].
31
19
18
16
Memory Base Address
(addr bits [31:19])
Address Mask (HW=0;
512 KB addr range)
15
4
3
2
1
0
Address Mask (cont)
(HW=0; 512 KB addr range)
Prefetch
Mem En
(HW=0)
Memory Type
(HW=0; 32 Mb addr)
Mem/IO
Space
(HW=0)
Bit
Description
31:19
Memory Base Address
[31:19].
R/W.
Set by the operating system, these bits correspond to address signals
18:4
Address Mask
RO.
Hardwired to 0s to indicate 512 KB address range.
3
Prefetchable Memory
RO.
Hardwired to 0 to prevent prefetching.
2:1
Memory Type
RO.
Hardwired to 0s to indicate 32-bit address.
0
Memory / IO Space
RO.
Hardwired to 0 to indicate memory space.
3.6.15.
SVID—Subsystem Vendor Identification Register (Device 2)
Address Offset:
2C
2Dh
Default Value:
0000h
Access:
Read/Write-Once
Size:
16 bits
Bit
Description
15:0
Subsystem Vendor ID—R/WO.
This value is used to identify the vendor of the subsystem. The
default value is 0000h. This field should be programmed by BIOS during boot-up. Once written, this
register becomes read-only. This Register can only be cleared by a Reset.