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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 94/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
94
Datasheet
3.5.16.
SSTS—Secondary PCI-PCI Status Register (Device 1)
Address Offset:
1E–1Fh
Default Value:
02A0h
Access:
Read-Only, Read/Write Clear
Size:
16 bits
SSTS is a 16-bit status register that reports the occurrence of error conditions associated with the
secondary side (i.e., PCI1/AGP side ) of the “virtual” PCI-PCI bridge embedded within GMCH.
15
14
13
12
11
10
9
8
Det. Parity
Error
Rec Sys
Error
(HW=0)
Rec
Master
Abort
Rec
Target
Abort
Sig Target
Abort
(HW=0)
DEVSEL Timing
(HW=01b; medium)
Data
Parity Det.
(HW=0)
7
6
5
4
0
FB2B
(HW=1)
Reserved
66/60 MHz
Cap
(HW=1)
Reserved
Bit
Descriptions
15
Detected Parity Error (DPE1).
Note that the function of this bit is not affected by the PERRE1 bit. Also
note that PERR# is not implemented in the GMCH.
1 = GMCH detected a parity error in the address or data phase of PCI1/AGP bus transactions.
0 =
Software sets DPE1 to 0 by writing a 1 to this bit.
14
Received System Error (SSE1).
Hardwired to 0. The GMCH does not have an SERR# signal pin.
13
Received Master Abort Status (RMAS1).
1 =
GMCH terminated a Host-to-PCI1/AGP with an unexpected master abort.
0 =
Software resets this bit to 0 by writing a 1 to it.
12
Received Target Abort Status (RTAS1).
1 =
GMCH-initiated transaction on PCI1/AGP is terminated with a target abort.
0 =
Software resets RTAS1 to 0 by writing a 1 to it.
11
Signaled Target Abort Status (STAS1).
Hardwired to 0. The GMCH does not generate target abort on
PCI1/AGP.
10:9
DEVSEL# Timing (DEVT1).
This 2-bit field indicates the timing of the DEVSEL# signal when the
GMCH responds as a target on PCI1/AGP, and is hard-wired to the value 01b (medium) to indicate the
time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.
8
Data Parity Detected (DPD1).
Hardwired to 0. GMCH does not implement G_PERR# function.
However, data parity errors are still detected and reported using SERR hub interface special cycles (if
enabled by SERRE1 and the BCTRL register, bit 0).
7
Fast Back-to-Back (FB2B1).
Hardwired to 1. The GMCH as a target supports fast back-to-back
transactions on PCI1/AGP.
6
Reserved.
5
66/
60 MHz
Capability.
Hardwired to 1.
4:0
Reserved.
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