參數(shù)資料
型號： FW82815
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 8/172頁
文件大?。?/td> 795K
代理商： FW82815
82815 GMCH
R
8
Datasheet
Figures
Figure 1. Intel
815 Chipset Family System Block Diagram ....................................................15
Figure 2. 82815 GMCH Block Diagram....................................................................................16
Figure 3. PAM Registers..........................................................................................................59
Figure 4. System Memory Address Map................................................................................122
Figure 5. Detailed Memory System Address Map..................................................................122
Figure 6. DRAM Array Sockets..............................................................................................139
Figure 7. GMCH Display Cache Interface to 4 MB.................................................................142
Figure 8. 3D/2D Pipeline Preprocessor..................................................................................144
Figure 9. Data Flow for the 3D Pipeline .................................................................................145
Figure 10. GMCH Pinout (Top View-Left Side)......................................................................156
Figure 11. GMCH Pinout (Top View-Right Side)....................................................................157
Figure 12. GMCH BGA Package Dimensions (Top and Side Views)....................................162
Figure 13. GMCH BGA Package Dimensions (Bottom View)................................................163
Figure 14. XOR Tree Implementation....................................................................................165
Tables
Table 1. Supported System Bus and System Memory Bus Frequencies ................................20
Table 2. GMCH PCI Configuration Space (Device 0)..............................................................42
Table 3. Supported System Memory DIMM Configurations.....................................................54
Table 4. Attribute Bit Assignments...........................................................................................58
Table 5. PAM Registers and Associated Memory Segments ..................................................59
Table 6. Summary of GMCH Error Sources, Enables and Status Flags .................................83
Table 7. GMCH Configuration Space (Device 1).....................................................................84
Table 8. Device 2 Configuration Space Address Map (Internal Graphics).............................102
Table 9. Memory Segments and Their Attributes...................................................................123
Table 10. Summay of Transactions Supported By GMCH.....................................................133
Table 11. Host Responses Supported by the GMCH ............................................................134
Table 12. Special Cycles........................................................................................................135
Table 13. Sample Of Possible Mix And Match Options For 4 Row/2 DIMM
Configurations........................................................................................................137
Table 14. Data Bytes on DIMM Used for Programming DRAM Registers.............................138
Table 15. GMCH DRAM Address Mux Function....................................................................139
Table 16. Programmable SDRAM Timing Parameters..........................................................140
Table 17. Memory Size for each configuration :.....................................................................142
Table 18. GMCH Local Memory Address Mapping................................................................143
Table 19. Partial List of Display Modes Supported ................................................................151
Table 20. Partial List of Flat Panel Modes Supported............................................................152
Table 21. Partial List of TV-Out Modes Supported ................................................................153
Table 22. Alphabetical Pin Assignment..................................................................................158
Table 23. Package Dimensions .............................................................................................163
Table 24. XOR Test Pattern Example....................................................................................166
Table 25 XOR Chain 1 35 Inputs Output: SMAA5 (A12)......................................................168
Table 26 XOR Chain 2 33 Inputs Output: SMAA2 (F12) ......................................................168
Table 27 XOR Chain 3 38 Inputs Output: SMAA0 (D13)......................................................169
Table 28 XOR Chain 4 36 Inputs Output: SMAA9 (D13)......................................................169
Table 29 XOR Chain 5 56 Inputs Output: SMD31 (K5) ........................................................170
Table 30 XOR Chain 6 60 Inputs Output: SMAA11 (A13)....................................................171
Table 31 XOR Chain 7 33 Inputs Output: SMAA8 (D12)......................................................171
Table 32 XOR Chain 8 31 Inputs Output: SMAA4 (B12)......................................................172
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