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82815 GMCH
R
Datasheet
121
4.
Functional Description
This chapter describes the Graphics and Memory Controller Hub (GMCH) interfaces, and boot
sequencing.. The “System Address Map” provides a system-level address memory map and describes the
memory space controls provided by the GMCH.
4.1.
System Address Map
An Intel
Pentium
III
processor, Intel
Pentium II processor, or Intel
Celeron
TM
processor system based
on the GMCH, supports 4 GB of addressable memory space and 64 KB+3 of addressable I/O space.
(The P6 bus I/O addressability is 64KB + 3). There is a programmable memory address space under the
1 MB region which can be controlled with programmable attributes of write-only, or read-only. Attribute
programming is described in the Configuration Register Description section. This section focuses on how
the memory space is partitioned and what these separate memory regions are used for. The I/O address
space is explained at the end of this section.
The Intel
Pentium
III
processor, Intel
Pentium II processor, and Intel
Celeron
TM
processor supports
addressing of memory ranges larger than 4 GB. The GMCH Host Bridge claims any access over 4 GB by
terminating transaction (without forwarding it to the hub interface). Writes are terminated by dropping
the data and for reads the GMCH returns all zeros on the host bus.
In the following sections, it is assumed that all of the compatibility memory ranges reside on the hub
interface. The exceptions to this rule are the VGA ranges which may be mapped to the internal Graphics
Device.
Note:
The GMCH memory map includes a number of programmable ranges. All of these ranges MUST be
unique and NON-OVERLAPPING. There are NO Hardware Interlocks to prevent problems in the case
of overlapping ranges. Accesses to overlapped ranges may produce indeterminate results.