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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 132/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
132
Datasheet
4.3.2.2.
Legacy VGA Ranges
The legacy VGA memory range A0000h–BFFFFh is mapped either to the hub interface or to AGP/PCI1
depending on the programming of the VGA Enable bit in the BCTRL configuration register in GMCH
Device #1 configuration space, and the MDAP bit in the GMCHCFG configuration register in Device #0
configuration space. The same register controls mapping VGA I/O address ranges. The VGA I/O range is
defined as addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA
address aliases: A[15:10] are not decoded). The function and interaction of these two bits is described
below:
MDA Present (MDAP):
This bit works with the VGA Enable bit in the BCTRL register of device 1 to
control the routing of processor-initiated transactions targeting MDA compatible I/O and memory
address ranges. This bit should not be set when the VGA Enable bit is not set. If the VGA enable bit is
set, accesses to IO address range x3BCh–x3BFh are forwarded to the hub interface. If the VGA enable
bit is not set, I/O address range accesses x3BCh–x3BFh are treated like other I/O accesses (the cycles are
forwarded to AGP if the address is within IOBASE and IOLIMIT and ISA enable bit is not set);
otherwise, they are forwarded to the hub interface. MDA resources are defined as the following:
Memory:
0B0000h–0B7FFFh
I/O:
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, are forwarded to the hub
interface, even if the reference includes I/O locations not listed above.
VGA Enable:
Controls the routing of processor-initiated transactions targeting VGA compatible I/O and
memory address ranges. When this bit is set, the GMCH forwards the following processor accesses to
AGP:
Memory accesses in the range 0A0000h to 0BFFFFh
I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(inclusive of ISA address aliases: A[15:10] are not decoded)
When this bit is set , forwarding of these accesses issued by the processor is independent of the I/O
address and memory address ranges defined by the previously defined Base and Limit registers.
Forwarding of these accesses is also independent of the settings of bit 2 (ISA Enable) of BCTRL if this
bit is 1. If the VGA enable bit is set, accesses to I/O address range x3BCh–x3BFh are forwarded to the
hub interface. If the VGA enable bit is not set, I/O address range accesses x3BCh–x3BFh are treated like
other I/O accesses (the cycles are forwarded to AGP, if the address is within IOBASE and IOLIMIT and
ISA enable bit is not set); otherwise, they are forwarded to the hub interface.
If this bit is 0 (default), VGA compatible memory and I/O range accesses are not forwarded to AGP;
rather, they are mapped to the hub interface, unless they are mapped to AGP via I/O and memory range
registers defined above (IOBASE, IOLIMIT, MBASE, MLIMIT, PMBASE, PMLIMIT).
The following table shows the behavior for all combinations of MDA and VGA:
VGA
MDA
Behavior
0
0
All references to MDA and VGA go to the hub interface
0
1
Illegal combination (DO NOT USE)
1
0
All references to VGA Go To AGP/PCI. MDA-only references (I/O Address 3BFh and
aliases) will go to the hub interface.
1
1
VGA references go to AGP/PCI; MDA references go to the hub interface.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
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