參數(shù)資料
型號(hào): FW82815
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù): 75/172頁(yè)
文件大小: 795K
代理商: FW82815
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82815 GMCH
R
Datasheet
75
3.4.30.
AGPCMD—AGP Command Register (Device 0: AGP Mode Only)
Address Offset:
A8–Abh
Default Value:
00000000h
Access:
Read/Write
Size:
32 bits
This register provides control of the AGP operational parameters.
31
10
9
8
Reserved
SBA EN
AGP EN
7
6
5
4
3
2
0
Reserved
4 GB
(HW=0)
FW EN
Reserved
Data Rate
Bit
Description
31:10
Reserved.
9
Sideband Address Enable (SBA).
1 = Enable. The sideband addressing mechanism is enabled.
0 = Disable
8
AGP Enable.
When this bit is reset to 0, the GMCH ignores all AGP operations, including the sync
cycle. Any AGP operations received while this bit is set to 1 will be serviced, even if this bit is reset to
0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being
delivered in 1X mode, the command is issued. When this bit is set to 1 the GMCH will respond to AGP
operations delivered via PIPE#, or to operations delivered via SBA, if the
AGP Side Band Enable bit is
also set to 1.
7:6
Reserved.
5
Greater Than 4 GB Support (4GB).
Hardwired to 0.
The GMCH as an AGP target does not support
addressing greater than 4 GB.
4
Fast Writes Enable (FW).
This bit must always be programmed to 0. The chipset will behave
unpredictably if this bit is programmed with 1.
3
Reserved.
2:0
Data Rate Capability.
The settings of these bits determines the AGP data transfer rate. One (
and only
one
) bit in this field must be set to indicate the desired data transfer rate. The same bit must be set on
both master and target. Configuration software will update this field by setting only one bit that
corresponds to the capability of AGP master (after that capability has been verified by accessing the
same functional register within the AGP master’s configuration space.)
Bit 0 = 1= 1X
Bit 1 = 1 = 2X
Bit 2 = 1 = 4x
Bit 2 becomes reserved (but will still read 4x, erroneously) when the 4x Override bit in the AGP CTRL
register is set to 1 because this bit will not be updated in 4x Override mode. When the 4x Override bit
is set writes to Data Rate[2] have no functional impact.
Note:
This field applies to AD and SBA buses.
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