參數(shù)資料
型號： FW82815
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 39/172頁
文件大?。?/td> 795K
代理商： FW82815
82815 GMCH
R
Datasheet
39
3.2.2.
Logical PCI Bus #0 Configuration Mechanism
The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONF_ADDR
register. If the Bus Number field of CONF_ADDR is 0, the configuration cycle is targeting a PCI Bus #0
device.
Device #0: The Host-hub interface Bridge/DRAM Controller entity within the GMCH is hardwired
as Device #0 on PCI Bus #0.
Device #1: The AGP interface entity within the GMCH is hardwired as Device #1 on PCI Bus #0.
Device #2: The internal graphics device entity within the GMCH is hardwired as Device #1 on PCI
Bus #0.
Note:
Configuration cycles to one of the GMCH internal devices are confined to the GMCH and not sent over
the hub interface. Note that accesses to devices #3 to #31 on PCI Bus #0 are forwarded over the hub
interface.
3.2.3.
Primary PCI (PCI0) and Downstream Configuration Mechanism
If the Bus Number in the CONF_ADDR is non-zero, the GMCH generates a configuration cycle over the
hub interface. The I/O Controller Hub compares the non-zero Bus Number with the Secondary Bus
Number and Subordinate Bus Number registers of its P2P bridges to determine if the configuration cycle
is meant for Primary PCI expansion bus (PCI0), or a downstream PCI bus.
3.2.4.
Internal Graphics Device Configuration Mechanism
From the chipset configuration perspective, the internal graphics device is seen as a PCI device
(device 2) on PCI Bus #0. Configuration cycles that target device 2 on PCI Bus #0 are claimed by the
internal graphics device and are not forwarded via hub interface to the I/O Controller Hub.
3.2.5.
GMCH Register Introduction
The GMCH contains two sets of software accessible registers, accessed via the Host I/O address space:
Control registers I/O mapped into the host I/O space that control access to PCI configuration space
(see section entitled I/O Mapped Registers)
Internal configuration registers residing within the GMCH are partitioned into three logical device
register sets (“l(fā)ogical” since they reside within a single physical device). The first register set is
dedicated to Host-hub interface Bridge/DRAM Controller functionality (controls PCI bus 0 such as
DRAM configuration, other chip-set operating parameters, and optional features). The second
register block is dedicated to the AGP interface and the third block is dedicated to the internal
graphics device in the GMCH.
The GMCH supports PCI configuration space accesses using the mechanism denoted as Configuration
Mechanism #1 in the PCI specification.
The GMCH internal registers (both I/O Mapped and Configuration registers) are accessible by the host.
The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of
CONF_ADDR which can only be accessed as a DWord. All multi-byte numeric fields use “l(fā)ittle-endian”
ordering (i.e., lower addresses contain the least significant parts of the field).
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