82815 GMCH
R
Datasheet
91
3.5.13.
SMLT—Secondary Master Latency Timer Register (Device 1)
Address Offset:
1Bh
Default Value:
00h
Access:
Read/Write
Size:
8 bits
This register controls the bus tenure of the GMCH on AGP/PCI. SMLT is an 8-bit register that controls
the amount of time the GMCH, as a AGP/PCI bus master, can burst data on the AGP/PCI Bus. The count
value is an 8-bit quantity; however, SMLT[2:0] are reserved and assumed to be 0 when determining the
count value. The GMCH’s SMLT is used to guarantee to the AGP master a minimum amount of the
system resources. When the GMCH begins the first PCI bus cycle after being granted the bus, the counter
is loaded and enabled to count from the assertion of FRAME#. If the count expires while the GMCH’s
grant is removed (due to AGP master request), the GMCH will lose the use of the bus and the AGP
master agent may be granted the bus. If the GMCH’s bus grant is not removed, the GMCH continues to
own the AGP/PCI bus, regardless of the SMLT expiration or idle condition. Note that the GMCH must
always properly terminate a AGP/PCI transaction, with FRAME# negation prior to the final data transfer.
The number of clocks programmed in the SMLT represents the guaranteed time slice (measured in
66 MHz PCI clocks) allotted to the GMCH, after which it must complete the current data transfer phase
and then surrender the bus as soon as its bus grant is removed. For example, if the SMLT is programmed
to 18h, the value is 24 AGP clocks. The default value of SMLT is 00h and disables this function. When
the SMLT is disabled, the burst time for the GMCH is unlimited (i.e., the GMCH can burst forever).
7
3
2
0
Secondary MLT Counter Value
Reserved
Bit
Description
7:3
Secondary MLT Counter Value.
Default=0 (i.e., SMLT disabled)
2:0
Reserved.