82815 GMCH
R
138
Datasheet
4.5.1.2.
DRAM Register Programming
This section provides an overview of how the required information for programming the DRAM registers
is obtained from the Serial Presence Detect ports on the DIMMs. The Serial Presence Detect ports are
used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by row basis),
SDRAM Timings, Row Sizes and Row Page Sizes. Table 14 lists a subset of the data available through
the on-board Serial Presence Detect ROM on each DIMM module.
Table 14. Data Bytes on DIMM Used for Programming DRAM Registers
Byte
Function
2
Memory Type (EDO, SDRAM) the GMCH only supports SDRAM.
3
# of Row Addresses, not counting Bank Addresses
4
# of Column Addresses
5
# of banks of DRAM (Single or Double sided) DIMM
12
Refresh Rate
17
# Banks on each SDRAM Device
36–41
Access Time from Clock for CAS# Latency 1 through 7
42
Data Width of SDRAM Components
Table 14 is only a subset of the defined SPD bytes on the DIMM module. These bytes collectively
provide enough data for BIOS to program the GMCH DRAM registers.
4.5.2.
DRAM Address Translation and Decoding
The GMCH translates the address received on the host bus, hub interface, or from the internal graphics
device to an effective memory address. The GMCH supports 16 Mbit and 64 Mbit SDRAM devices. The
GMCH supports a 2 KB page sizes only. The multiplexed row / column address to the DRAM memory
array is provided by the SBS[1:0] and SMAA[11:0] signals and copies. These addresses are derived from
the host address bus as defined by by the following table for SDRAM devices.
Row size is internally computed using the values programmed in the DRP register.
Up to 4 pages can be open at any time within any row (Only 2 active pages are supported in rows
populated with either 8 MBs or 16 MBs ).