82815 GMCH
R
84
Datasheet
3.5.
AGP/PCI Bridge Registers
(Device 1: Visible in AGP Mode Only)
These registers are accessible through the configuration mechanism defined in an earlier section of this
document.
Table 7. GMCH Configuration Space (Device 1)
Address
Offset
Mnemonic
Register Name
Default Value
Access
Type
00–01h
VID1
Vendor Identification
8086h
RO
02–03h
DID1
Device Identification
1131h
RO
04–05h
PCICMD1
PCI Command
0000h
RO, R/W
06–07h
PCISTS1
PCI Status
0020h
RO, R/WC
08
RID1
Revision Identification
02h (see note)
RO
09
Reserved
00h
0Ah
SUBC1
Sub-Class Code
04h
RO
0Bh
BCC1
Base Class Code
06h
RO
0Ch
Reserved
00h
0Dh
MLT1
Master Latency Timer
00h
R/W
0Eh
HDR1
Header Type
01h
RO
0F–17h
Reserved
00h
18h
PBUSN
Primary Bus Number
00h
RO
19h
SBUSN
Secondary Bus Number
00h
R/W
1Ah
SUBUSN
Subordinate Bus Number
00h
R/W
1Bh
SMLT
Secondary Bus Master Latency Timer
00h
R/W
1Ch
IOBASE
I/O Base Address
F0h
R/W
1Dh
IOLIMIT
I/O Limit Address
00h
R/W
1E–1Fh
SSTS
Secondary Status
02A0h
RO, R/WC
20–21h
MBASE
Memory Base Address
FFF0h
R/W
22–23h
MLIMIT
Memory Limit Address
0000h
R/W
24–25h
PMBASE
Prefetchable Memory Base Address
FFF0h
R/W
26–27h
PMLIMIT
Prefetchable Memory Limit Address
0000h
R/W
28–3Dh
Reserved
00h
3Eh
BCTRL
Bridge Control
00h
R/W
3Fh
Reserved
00h
40h
ERRCMD1
Error Command
00h
R/W
41–FFh
Reserved
00h
Note:
See Specification Update document for latest information.