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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 130/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
130
Datasheet
4.3.2.
Address Decode Rules
The GMCH accepts all memory read and write accesses from the hub interface to both system memory
and graphics memory. The hub interface accesses that fall elsewhere within the PCI memory range will
not be accepted. The GMCH never responds to hub interface initiated I/O read or write cycles.
The GMCH accepts accesses from the hub interface to the following address ranges:
All memory read and write accesses to main DRAM including PAM region (except SMM space)
All memory read/write accesses to the graphics aperture (DRAM) defined by APBASE and
APSIZE.
All hub interface memory write accesses to AGP memory range defined by MBASE, MLIMIT,
PMBASE, and PMLIMIT.
Memory writes to VGA range on AGP, if enabled.
The hub interface memory accesses that fall elsewhere within the memory range are considered invalid
and will be remapped to a translated memory address, snooped on the host bus, and dispatched to
DRAM. Reads will return all 1s with Master Abort completion. Writes will have byte enables deasserted
and will terminate with Master Abort, if completion is required. I/O cycles will not be accepted. They are
terminated with Master Abort completion packets.
The Hub Interface Accesses to GMCH that Cross Device Boundaries
The hub interface accesses are limited to 256 bytes but have no restrictions on crossing address
boundaries. A single hub interface request may, therefore, span device boundaries (AGP, DRAM) or
cross from valid addresses to invalid addresses (or vica versa). The GMCH does not support transactions
that cross device boundaries. For reads and for writes requiring completion, the GMCH provides
separate completion status for each naturally-aligned 32 or 64 byte block. If the starting address of a
transaction hits a valid address, the portion of a request that hits that target device (AGP or DRAM) will
complete normally.
The remaining portion of the access that crosses a device boundary (targets a different device than that of
the starting address) or hits an invalid address will be remapped to memory address 0h, snooped on the
host bus, and dispatched to DRAM. Reads will return all 1s with Master Abort completion. Writes will
have byte enables deasserted and will terminate with Master Abort if completion is required.
If the starting address of a transaction hits an invalid address, the entire transaction will be remapped to
memory address 0h, snooped on the host bus, and dispatched to DRAM. Reads will return all 1s with
Master Abort completion. Writes will have byte enables deasserted and will terminate with Master Abort
if completion is required.
相關(guān)PDF資料 |
PDF描述 |
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| FWA-25A10F | Fuse |
| FWA-30A10F | Fuse |
| FWA-35A21F | Fuse |
| FWA-40A21F | Fuse |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
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