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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 11/172頁(yè) |
| 文件大小： | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
11
82815 GMCH Features
!
Intel
Pentium
III
processor and Intel
Celeron
Processor in FC-PGA package
Supports processor 370-Pin Socket
Supports 32-Bit System Bus Addressing
4 deep in-order queue; 4 or 1 deep request queue
Supports Uni-processor systems only
In-order and Dynamic Deferred Transaction Support
66/100/133MHz System Bus Frequency
GTL+ I/O Buffer
!
32 MB to 512 MB using 16Mb/64Mb/128Mb/256Mb
technology
Supports up to 3 double sided DIMMs at 100 MHz system
memory bus
Supports up to 2 double sided or 3 single sided DIMMs at
133 MHz system memory bus.
64-bit data interface
100/133 MHz system memory bus frequency
Support for Asymmetrical SDRAM addressing only
Support for x8 and x16 SDRAM device width
Unbuffered, Non-ECC SDRAM only supported
Refresh Mechanism: CBR ONLY supported
Enhanced Open page arbitration SDRAM paging scheme
Suspend to RAM support
!
Internal Graphics
Supports a single AGP device via a connector
Supports AGP 2.0 including 4x AGP data transfers
AGP Universal Connector support via dual mode buffers
to allow AGP 2.0 3.3V or 1.5V signaling
AGP PIPE# or SBA initiated accesses to SDRAM not
snooped
AGP FRAME# initiated accesses to SDRAM are snooped
High priority access support
Hierarchical PCI configuration mechanism
Delayed transaction support for AGP-to-SDRAM reads
that can not be serviced immediately
!
Intelligent Centralized Arbitration Model for Optimum
Concurrency Support
Concurrent operations of processor and System busses
supported via dedicated arbitration and data buffering
!
Distributed Data Buffering Model for optimum
concurrency
SDRAM Write Buffer with read-around-write capability
Dedicated processor –SDRAM, hub interface-SDRAM
and Graphics-SDRAM Read Buffers
!
SMRAM space remapping to A0000h (128 KB)
Optional Extended SMRAM space above 256 MB,
additional 512 KB / 1MB TSEG from Top of Memory,
cacheable
Stop Clock Grant and Halt special cycle translation from
the host to the hub interface
ACPI Compliant power management
APIC Buffer Management
SMI, SCI, and SERR error indication
!
Controller
3D Hyper Pipelined Architecture
-Parallel Data Processing (PDP)
-Precise Pixel Interpolation (PPI)
Full 2D H/W Acceleration
Motion Video Acceleration
Supports 133 MHz System Memory while running in
non-CPC mode
!
Flat & Gouraud Shading
Mip Maps with Trilinear and Anisotropic Filtering
Full Color Specular
Fogging Atmospheric Effects
Z Buffering
3D Pipe 2D Clipping
Backface Culling
!
Per Pixel Perspective Correction Texture Mapping
Texture Compositing
Texture Color Keying/Chroma Keying
!
85 MHz Flat Panel Monitor/Digital CRT Interface Or
Digital Video Output for use with a external TV encoder
!
Integrated 24-bit 230 MHz RAMDAC
Gamma Corrected Video
DDC2B Compliant
!
Up to 1600x1200 in 8-bit Color at 85 Hz Refresh
Hardware Accelerated Functions
3 Operand Raster BitBLTs
64x64x3 Color Transparent Cursor
!
H/W Motion Compensation Assistance for S/W MPEG2
Decode
Software DVD at 30 fps
Digital Video Out Port
NTSC and PAL TV Out Support
H/W Overlay Engine with Bilinear Filtering
Independent gamma correction, saturation, brightness &
contrast for overlay
!
Intel
D.V.M. Technology
!
32-bit data interface
133 MHz SDRAM interface only.
Flexible AGP In-Line Memory Module (AIMM)
Implementation
Support for 2 1Mx16, or 1 2Mx32 on AIMM card
4 MB maximum addressable
!
82801AA I/O Controller Hub (ICH)
82801BA I/O Controller Hub (ICH2)
!
544 BGA
1.85V core with 3.3V CMOS I/O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
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