參數(shù)資料
型號： FW82815
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 137/172頁
文件大?。?/td> 795K
代理商： FW82815
82815 GMCH
R
Datasheet
137
Table 13 illustrates a sample of the possible DIMM socket configurations along with corresponding DRP
programming. See the register section of this document for a complete DRP programming table.
Table 13. Sample Of Possible Mix And Match Options For 4 Row/2 DIMM Configurations
DIMM0
DIMM1
DRP
Total Memory
0
4x(4M x 16 ) S
70
32 MB
4x (4M x16 ) S
0
07
32 MB
4x(4Mx16) + 2x(2Mx32) D
0
08
48 MB
4x(4Mx16) S
4x(4Mx16) S
77
64 MB
8x(8Mx8) + 4x(4Mx16) D
0
0B
96 MB
8x(8Mx8) D
0
0C
128 MB
8x(8Mx8) D
8x(8Mx8) D
CC
256 MB
NOTES:
1. “S” denotes single-sided DIMMs, “D” denotes double-sided DIMMs.
4.5.1.1.
Configuration Mechanism For DIMMs
Detection of the type of DRAM installed on the DIMM is supported via Serial Presence Detect
mechanism as defined in the JEDEC 168-pin DIMM standard. This standard uses the SCL, SDA and
SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special
programmable modes are provided on the GMCH for detecting the size and type of memory installed.
Type and size detection must be done via the serial presence detection pins. Use of Serial Presence
Detection is required.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the GMCH DRAM registers must be
initialized. The GMCH must be configured for operation with the installed memory types. Detection of
memory type and size is done via the System Management Bus (SMBus) interface on the I/O Controller
Hub. This two wire bus is used to extract the DRAM type and size information from the serial presence
detect port on the DRAM DIMM modules.
DRAM DIMM modules contain a 5-pin serial presence detect interface, including SCL (serial clock),
SDA (serial data) and SA[2:0]. Devices on the SMBus bus have a seven bit address. For the DRAM
DIMM modules, the upper four bits are fixed at 1010. The lower three bits are strapped on the SA[2:0]
pins. SCL and SDA are connected directly to the System Management Bus on the I/O Controller Hub.
Thus, data is read from the Serial Presence Detect port on the DRAM DIMM modules via a series of IO
cycles to the I/O Controller Hub. BIOS essentially needs to determine the size and type of memory used
for each of the four rows of memory in order to properly configure the GMCH system memory interface.
SMBus Configuration and Access of the Serial Presence Detect Ports
For more details on this, see the
Intel
82801AA (ICH) and Intel
82801AB (ICH0) I/O Controller Hub
datasheet or
Intel
82801BA (ICH2) I/O Controller Hub
datasheet
..
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