參數(shù)資料
型號(hào)： FW82815
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 89/172頁
文件大?。?/td> 795K
代理商： FW82815
82815 GMCH
R
Datasheet
89
3.5.8.
MLT1—Master Latency Timer Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
Read/Write
8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to prevent standard PCI-PCI bridge configuration software from getting “confused”.
Bit
Description
7:3
Not applicable but supports read/write operations.
(Reads return previously written data.)
2:0
Reserved.
3.5.9.
HDR1—Header Type Register (Device 1)
Address Offset:
Default:
Access:
Size:
0Eh
01h
Read-Only
8 bits
This register identifies the header layout of the configuration space. No physical register exists at this
location.
Bit
Descriptions
7:0
This read-only field always returns 01h when read. Writes have no effect.
3.5.10.
PBUSN—Primary Bus Number Register (Device 1)
Address Offset:
18h
Default:
00h
Access:
Read-Only
Size:
8 bits
This register identifies that the “virtual” PCI-PCI bridge is connected to bus #0.
Bit
Descriptions
7:0
Bus Number.
Hardwired to 0.
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