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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 23/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
23
Signal Name
Type
Description
RS[2:0]#
I/O
AGTL+
Response Signals.
Indicates type of response as shown below:
000 = Idle state
001 = Retry response
010 = Deferred response
011 = Reserved (not driven by the GMCH)
100 = Hard Failure (not driven by the GMCH)
101 = No data response
110 = Implicit Writeback
111 = Normal data response
GTLREF[1:0]
I
GTL Reference.
Reference voltage input for the Host GTL interface. GTLREF is
2/3 * VTT. VTT is nominally 1.5V.
2.2.
System Memory Interface Signals
Signal Name
Type
Description
SMAA[12:0]
SMAB[7:4]#
SMAC[7:4]#
SBS[1:0]
O
CMOS
Memory Address.
SMAA[12:0], SMAB[7:4]#, and SMAC[7:4]# are used to provide
the multiplexed row and column address to SDRAM. SBS[1:0] provide the Bank
Select.
SBS[1:0]
O
CMOS
Memory Bank Select.
These signals define the banks that are selected within
each DRAM row. The SMAx and SBS signals combine to address every possible
location within a DRAM device.
SBS[1:0] may be heavily loaded and require 2 SDRAM clock cycles for setup time
to the SDRAMs. For this reason, all chip select signals (SCSA[5:0]# and
SCSB[5:0]#) must be deasserted on any SDRAM clock cycle that one of these
signals change.
SMD[63:0]
I/O
CMOS
Memory Data.
These signals are used to interface to the SDRAM data bus.
SDQM[7:0]
O
CMOS
Input/Output Data Mask.
These pins act as synchronized output enables during
read cycles and as a byte enables during write cycles.
SCSA[5:0]#
SCSB[5:0]#
O
CMOS
Chip Select.
For the memory row configured with SDRAM, these pins perform the
function of selecting the particular SDRAM components during the active state.
SRAS#
O
CMOS
SDRAM Row Address Strobe.
These signals drive the SDRAM array directly
without any external buffers.
SCAS#
O
CMOS
SDRAM Column Address Strobe.
These signals drive the SDRAM array directly
without any external buffers.
SWE#
O
CMOS
Write Enable Signal.
SWE# is asserted during writes to SDRAM.
SCKE[5:0]
O
CMOS
System Memory Clock Enable.
SCKE SDRAM Clock Enable is used to signal a
self-refresh or power-down command to an SDRAM array when entering system
suspend.
SRCOMP
O
System Memory RCOMP.
Used to calibrate the System memory I/O buffers. This
pin should be connected to a 40 ohm resistor tied to 3.3V VCC (VSUS3.3).
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