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82815 GMCH
R
Datasheet
105
3.6.4.
PCISTS2—PCI Status Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
06h
07h
02B0h
Read-Only
16 bits
PCISTS2 reports the occurrence of a PCI compliant master abort and PCI compliant target abort.
PCISTS2 also indicates the DEVSEL# timing that has been set by the GMCH hardware.
15
14
13
12
11
10
9
8
Detected
Par Error
(HW=0)
Sig Sys
Error
(HW=0)
Recog
Mast Abort
Sta
(HW=0)
Rec
Target
Abort Sta
(HW=0)
Sig Target
Abort Sta
(HW=0)
DEVSEL# Timing
(HW=01)
Data Par
Detected
(HW=0)
7
6
5
4
3
0
FB2B
(HW=1)
User Def
Format
(HW=0)
66 MHz
PCI Cap
(HW=1)
Cap List
(HW=1)
Reserved
Bits
Description
15
Detected Parity Error (DPE)
RO.
Hardwired to 0. The chipset does not detect parity.
14
Signaled System Error (SSE)
SERR#.
RO.
Hardwired to 0.
The chipset’s graphics device never asserts
13
Received Master Abort Status (RMAS)
gets a Master Abort.
RO.
Hardwired to 0.
The chipset’s graphics device never
12
Received Target Abort Status (RTAS)
gets a Target Abort.
RO.
. Hardwired to 0.
The chipset’s graphics device never
11
Signaled Target Abort Status (STAS).
Hardwired to 0. The chipset does not use target abort
semantics.
10:9
DEVSEL# Timing (DEVT)
GMCH responds as a target.
RO.
This 2-bit field indicates the timing of the DEVSEL# signal when
01 = Medium decode device (hardwired).
8
Data Parity Detected (DPD)
disabled (and GMCH does not do any parity detection), this bit is not used
.
RO.
Hardwired to 0. Since Parity Error Response is hardwired to
7
Fast Back-to-Back (FB2B).
Hardwired to 1. The chipset accepts fast back-to-back when the
transactions are not to the same agent.
6
User Defined Format (UDF).
Hardwired to 0.
5
66 MHz PCI Capable (66C).
Hardwired to 1. This indicates that the chipset is 66 MHz PCI capable.
4
CAP LIST
function’s PCI Configuration Space containing a pointer to the location of the first item in the list.
RO.
This bit is set to 1 to indicate that the register at 34h provides an offset into the
3:0
Reserved.