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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 28/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
28
Datasheet
Signal Name
Type
Description
G_DEVSEL#
I/O
s/t/s
AGP
Device Select.
During PIPE# and SBA Operation.
This signal is
not used
during PIPE# or SBA
operation.
During FRAME# Operation.
G_DEVSEL#, when asserted, indicates that a
FRAME# based AGP target device has decoded its address as the target of the
current access. The GMCH asserts G_DEVSEL# based on the SDRAM address
range being accessed by a PCI initiator. As an input it indicates whether any device
on the bus has been selected.
G_REQ#
I
AGP
Request.
During SBA Operation.
This signal is
not used
during SBA operation.
During PIPE# and FRAME# Operation.
G_REQ#, when asserted, indicates that a
FRAME# or PIPE# based AGP master is requesting use of the AGP interface. This
signal is an input into the GMCH.
G_GNT#
O
AGP
Grant.
During SBA, PIPE# and FRAME# Operation.
G_GNT# along with the information
on the ST[2:0] signals (status bus) indicates how the AGP interface will be used
next. Refer to the AGP Interface Specificaiton revision 2.0 for further explanation of
the ST[2:0] values and their meanings.
G_AD[31:0]
I/O
AGP
Address/Data Bus.
During PIPE# and FRAME# Operation.
G_AD[31:0] are used to transfer both
address and data information on the AGP inteface.
During SBA Operation.
G_AD[31:0] are used to transfer data on the AGP
interface.
G_C/BE[3:0]#
I/O
AGP
Command/Byte Enable.
During FRAME# Operation.
During the address phase of a transaction,
G_C/BE[3:0]# define the bus command. During the data phase G_C/BE[3:0]# are
used as byte enables. The byte enables determine which byte lanes carry
meaningful data. The commands issued on the G_C/BE# signals during FRAME#
based AGP are the same G_C/BE# command described in the PCI 2.1 and 2.2
specifications.
During PIPE# Operation.
When an address is enqueued using PIPE#, the C/BE#
signals carry command information. Refer to the AGP 2.0 Interface Specification
Revision 2.0 for the definition of these commands. The command encoding used
during PIPE# based AGP is
Different
than the command encoding used during
FRAME# based AGP cycles (or standard PCI cycles on a PCI bus).
During SBA Operation.
These signals are not used during SBA operation.
G_PAR
I/O
AGP
Parity.
During FRAME# Operation.
G_PAR is driven by the GMCH when it acts as a
FRAME# based AGP initiator during address and data phases for a write cycle, and
during the address phase for a read cycle. G_PAR is driven by the GMCH when it
acts as a FRAME# based AGP target during each data phase of a FRAME# based
AGP memory read cycle. Even parity is generated across G_AD[31:0] and
G_C/BE[3:0]#.
During SBA and PIPE# Operation.
This signal is not used during SBA and PIPE#
operation.
NOTES:
1. LOCK#, SERR#, and PERR# signals are not supported on the AGP Interface (even for PCI operations).
2. PCI signals described in this table behave according to PCI 2.1 specifications when used to perform PCI
transactions on the AGP interface.
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