- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄370261 > FW82815 Controller Miscellaneous - Datasheet Reference PDF資料下載
參數(shù)資料
| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 82/172頁(yè) |
| 文件大小： | 795K |
| 代理商： | FW82815 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)當(dāng)前第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)
82815 GMCH
R
82
Datasheet
3.4.37.
ERRCMD—Error Command Register
(Device 0: AGP Mode Only)
Address Offset:
Default Value:
Access:
Size:
CBh
00h
Read/Write
8 bits
This register enables various errors to generate a SERR hub interface special cycle. Since the GMCH
does not have an SERR# signal, SERR messages are passed from the GMCH to the I/O Controller Hub
over the hub interface. The actual generation of the SERR message is globally enabled for Device 0 via
the PCI Command register.
Note:
An error can generate one and only one hub interface error special cycle. It is software’s responsibility to
make sure that when an SERR error message is enabled for an error condition, SMI and SCI error
messages are disabled for that same error condition.
7
6
5
4
3
2
1
0
Reserved
SRMMRO
SRTA
SLNDM
SAAOGA
SIAA
SAIGATTE
Bit
Description
7:6
Reserved.
5
SERR on Receiving Main Memory Refresh Overrun Enable.
Identical functionality in Device 2
memory mapped space @ 020B8h. This bit allows use of this same functionality in AGP Mode.
1 = Enable.
GMCH generates a SERR hub interface special cycle when a main memory refresh
overrun occurs.
0 = Disable. Reporting of this condition is disabled.
4
SERR on Receiving Target Abort on the hub interface.
1 = Enable.
GMCH generates a SERR hub interface special cycle when a GMCH-originated hub
interface cycle is terminated with a Target Abort.
0 = Disable. Reporting of this condition is disabled.
3
SERR on LOCK to non-DRAM Memory.
1 = Enable. GMCH generates a SERR hub interface special cycle when a processor-initiated LOCK
transaction targeting non-DRAM memory space occurs.
0 = Disable. Reporting of this condition is disabled.
2
SERR on AGP Access Outside of Graphics Aperture.
1 = Enable. GMCH generates a SERR hub interface special cycle when an AGP access occurs to an
address outside of the graphics aperture.
0 = Disable. Reporting of this condition is disabled.
1
SERR on Invalid AGP Access.
1 = Enable. GMCH generates a SERR hub interface special cycle when an AGP access occurs to an
address outside of the graphics aperture and either to the 640 KB–1 MB range or above the top of
memory.
0 = Disable.
0
SERR on Access to Invalid Graphics Aperture Translation Table Entry.
1 = Enable. GMCH generates a SERR hub interface special cycle when an invalid translation table
entry was returned in response to a AGP access to the graphics aperture.
0 = Disable. Reporting of this condition via SERR messaging is disabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FWA-25A10F | Fuse |
| FWA-30A10F | Fuse |
| FWA-35A21F | Fuse |
| FWA-40A21F | Fuse |
| FWA-45A21F | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。