參數(shù)資料
型號(hào)： FW82815
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 141/172頁
文件大小： 795K
代理商： FW82815
82815 GMCH
R
Datasheet
141
4.7.
Display Cache Interface
The GMCH Display Cache (DC) is a single channel 32-bit wide SDRAM interface. The GMCH handles
the control and timing for the display cache. The display cache interface of the GMCH generates the
LCS#, LDQM[7:0], LSCAS#, LSRAS#, LWE#, LMD[31:0] and multiplexed addresses, LMA[11:0] for
the display cache DRAM array. The GMCH also generates the clock LTCLK[1:0] for write cycles as
well as LOCLK for read cycle timings.
The display cache interface of the GMCH supports single data rate synchronous dynamic random access
memory (SDRAM). It supports a single 32-bit wide memory channel. The interface handles the operation
of D.V.M. with DC at 133 MHz. The DRAM controller interface is fully configurable through a set of
control registers.
Internal buffering (FIFOs) of the data to and from the display cache ensures the synchronization of the
data to the internal pipelines. The D.V.M. with DC interface clocking is divided synchronous with
respect to the core and system bus.
The display cache resides on an AGP In-Line Memory Module (AIMM). The startup sequencing for the
AIMM (which is interfaced via the AGP connector), is as follows:
1. System BIOS detects if an AGP card is present by performing a configuration read to PCI. If an
AGP card is present, it becomes the display device and bit 0 of the APCONT register should be set
to 0. No further initialization of internal graphics will take place. If internal graphics is the
preferred display device, bit 0 of the APCONT register should be set to 1. If no AGP card is
present, the internal graphics becomes the display device and bit 0 of the APCONT register should
be set to 1. PCI enumeration takes place at this point.
In the case where internal graphics is selected, the remaining steps still apply:
2. System BIOS determines if an AIMM card (local memory) is present.
If the AIMM card is present, the following steps take place:
3. Local Memory Clock Frequency is determined with a reset strap (on AGP pin SBA[7]) sampled as
an input during reset.
4. Memory Timing Options will be determined empirically by the system BIOS. BIOS will start with
programming slow timings (CAS Latency, RAS Pre-charge, etc.) and then trying faster timings
until it breaks. The settings that optimize performance without compromising functionality will be
selected.
4.7.1.
Supported DRAM Types for Display Cache Memory
The GMCH supports 1Mx16 and 2Mx32 SDRAMs; however, the GMCH only supports 4 MB of display
cache.
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